MRAM is rapidly replacing conventional memory. One critical aspect of the MRAM technology development is forming a magnetic tunnel junction (MTJ) structure for MTJ memory devices. However, conventional etching processes may remove and damage a shallow and small top electrode (TE) of a MTJ structure, thereby significantly damaging the operation of a memory device. For example, the critical dimension (CD) of a shallow and small MTJ TE is approximately 40 nanometer (nm); however, the process variation from chemical mechanical planarization (CMP) and etching is more than 40 nm. Therefore, there is no manufacturing process window. In addition, MTJ sidewalls are commonly formed of silicon nitride (SiN), which is low temperature and has lower oxide etch selectivity compared with normal SiN. Consequently, the likelihood of damage to the thin MTJ sidewalls and compromised MTJ performance is significantly increased.
A need therefore exists for methodology enabling fabrication of a MTJ TE that addresses the top connection challenges when the MTJ TE is shallow and small and the resulting device.